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19-3683; Rev 0; 5/05
Multiple-Output Clock Generator with Spread Spectrum
General Description
The MAX9492 frequency synthesizer is designed to generate multiple clocks for clock distribution in network routers or switches. The device provides a total of six buffered clock outputs (CLK1 to CLK6). CLK1 is the buffered output of the reference clock. CLK2 through CLK6 are independently programmable to generate eight different frequencies based on a 25MHz input crystal: 133, 125, 83, 66, 62.5, 50, 33, and 25MHz. All the outputs are LVCMOS single-ended signals. Either a 25MHz crystal or an external clock can serve as the input reference clock. The MAX9492 incorporates two phase-locked loops (PLLs) with two internal loop filters. Select the MAX9492's output clock frequency by programming on-chip registers through the MAX9492's I2C* interface. The device also features spread-spectrum capability to reduce electromagnetic interference (EMI). This technique allows spreading the fundamental energy over a wider frequency range, hence reducing the respective energy amplitude. The output frequency spectrum is downspread by -1.25% or -2.5%. The MAX9492 operates from a 3.3V supply and is guaranteed over the extended temperature range (-40C to +85C). The device is available in a space-saving, 20-pin, TQFN, 5mm x 5mm package.
Features
o Five LVCMOS Outputs with Independent Frequency Selections o One Buffered Reference Clock Output o Eight Selectable Frequencies: 133, 125, 83, 66, 62.5, 50, 33, and 25MHz o Crystal or an Input-Clock-Based Clock Reference o Output Frequency Programmed Through I2C Interface o 0, -1.25%, or -2.5% Selectable Downspreading Rate o Low Output Period Jitter (Without Spread Spectrum) < 10psRMS o <220ps Output-to-Output Skew o Available in 20-Lead, 5mm x 5mm, TQFN Package o +3.3V Supply o -40C to +85C Extended Temperature Range
MAX9492
Applications
Network Routers Telecom/Networking Equipment Storage Area Networks/Network Attached Storage
PART TEMP RANGE
Ordering Information
PINPACKAGE PKG CODE T2055-3
20 Thin QFN-EP** MAX9492ETP -40C to +85C 5mm x 5mm x 0.8mm
**EP = Exposed pad.
Typical Operating Circuit and Pin Configuration appear at end of data sheet.
*Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Multiple-Output Clock Generator with Spread Spectrum MAX9492
ABSOLUTE MAXIMUM RATINGS
VDD_ to GND .........................................................-0.3V to +4.0V All Other Pins to GND.................................-0.3V to (VDD + 1.0V) Short-Circuit Duration (all LVCMOS outputs) .............Continuous ESD Protection (Human Body Model)................................. 2kV Continuous Power Dissipation (TA = +70C) 20-Pin TQFN (derate 20.8mW/C above +70C) ......1667mW Storage Temperature Range .............................-65C to +165C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VDD = VDDA = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values at VDD = VDDA = +3.3V, TA = +25C, with CLK1 at 25MHz, and all other CLK_ outputs at 133MHz.) (Note 1)
PARAMETER CLOCK INPUT (X1) Input High Level Input Low Level Input Current CLOCK OUTPUTS (CLK_) Output High Level VOH IOH = -100A IOH = -4mA Output Low Level Output Short-Circuit Current Output Capacitance Input High Level Input Low Level Input Open Level Input Current VOL IOS CO VIH2 VIL2 VIO2 IIL2, IIH2 VIL2 = 0 or VIH2 = VDD 1.35 -15 0.7 x VDD 0.3 x VDD -1 ISINK = 4mA (Note 2) 3.0 3.0 CL = 10pF All clock registers = 0x0F 60 18 +1 0.4 10 3.6 3.6 76 24 IOL = 100A IOL = 4mA CLK_ = VDD or GND (Note 2) 2.5 0.8 1.90 +15 -60 VDD 0.2 2.4 0.2 0.4 +69 5 V mA pF V V V A V VIH1 VIL1 IIL1, IIH1 VX_ = 0 to VDD -20 2.0 0.8 +20 V V A SYMBOL CONDITIONS MIN TYP MAX UNITS
THREE-LEVEL INPUTS (SSC, SA0, SA1)
SERIAL INTERFACE (SCL, SDA) (Note 3) Input High Level Input Low Level Input Leakage Current Low-Level Output Input Capacitance POWER SUPPLIES Digital Power-Supply Voltage Analog Power-Supply Voltage Total Supply Current Output Disabled Supply Current VDD VDDA IDC IOD V V mA mA VIH VIL IIH, IIL VOL Ci V V A V pF
2
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Multiple-Output Clock Generator with Spread Spectrum
AC ELECTRICAL CHARACTERISTICS
(VDD = VDDA = +3.0V to +3.6V, CL = 10pF, unless otherwise noted. Typical values at VDD = VDDA = +3.3V, TA = +25C, with CLK1 at 25MHz and all other CLK_ outputs at 133MHz.) (Note 2)
PARAMETER OUTPUTS (CLK_) Crystal Frequency Input Frequency Range Crystal Frequency Tolerance Output-to-Output Skew Rise Time Fall Time Duty Cycle Output Period Jitter Power-Up Time Frequency Spread JP tPO RMS (SSC = 0), CLK1 is disabled to high impedance VDD > 2.8V to PLL lock SSC = high SSC = floating fA tSKO tR1 tF1 Any two CLK_ outputs 20% VDD to 80% VDD 80% VDD to 20% VDD 40 10 2 -2.5 -1.25 1.9 1.3 External clock 10 15 -50 35 35 +50 220 2.5 2.5 60 15 MHz MHz ppm ps ns ns % ps ms % SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9492
SERIAL INTERFACE TIMING
(VDD = VDDA = +3.3V, TA = -40C to +85C.) (Note 1, Figure 1)
PARAMETER Serial Clock Bus Free Time Between STOP and START Conditions Hold Time, Repeated START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Hold Time Slave Data Setup Time SCL Clock Low Period SCL Clock High Period Rise Time of SDA and SCL, Receiving Fall Time of SDA and SCL, Receiving SYMBOL fSCL tBUF tHD,STA tSU,STA tSU,STO tHD,DAT tHD,DAT tSU,DAT tLOW tHIGH tR tF (Notes 2, 5) (Notes 2, 5) (Note 4) (Note 4) 1.3 0.6 0.6 0.6 15 15 100 1.3 0.7 20 + 0.1CB 20 + 0.1CB 300 300 900 900 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s ns ns ns s s ns ns
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Multiple-Output Clock Generator with Spread Spectrum MAX9492
SERIAL INTERFACE TIMING (continued)
(VDD = VDDA = +3.3V, TA = -40C to +85C.) (Note 1, Figure 1)
PARAMETER Fall Time of SDA, Transmitting Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line SYMBOL tF,TX tSP CB (Notes 2, 6) (Notes 2, 7) (Note 2) CONDITIONS MIN 20 + 0.1CB 0 TYP MAX 250 50 400 UNITS ns ns pF
Note 1: All DC parameters tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. Note 3: No high output level is specified but only the output resistance to the bus. For I2C, the high-level voltage is provided by pullup resistors on the bus. Note 4: The device provides a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL's falling edge. Note 5: CB = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x VDD. Note 6: Bus sink current is less than 6mA. CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 x VDD and 0.7 x VDD. Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE (ALL OUTPUTS SET TO 133MHz)
MAX9492 toc01
RISE TIME vs. TEMPERATURE (ALL OUTPUTS SET TO 133MHz)
MAX9492 toc02
FALL TIME vs. TEMPERATURE (ALL OUTPUTS SET TO 133MHz)
MAX9492 toc03
62.0 61.6 61.2 SUPPLY CURRENT (mA) 60.8 60.4 60.0 59.6 59.2 58.8 58.4 58.0 -40 -15 10 35 TEMPERATURE (C) 60
2.5
2.0
2.3 RISE TIME (ns)
1.8 FALL TIME (ns)
2.1
1.6
1.9
1.4
1.7
1.2
1.5 85 -40 -15 10 35 TEMPERATURE (C) 60 85
1.0 -40 -15 10 35 TEMPERATURE (C) 60 85
4
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Multiple-Output Clock Generator with Spread Spectrum MAX9492
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
PERIOD JITTER vs. TEMPERATURE
MAX9492 toc04
133MHz OUTPUT WAVEFORM
MAX9492 toc05
83MHz OUTPUT WAVEFORM
MAX9492 toc06
20
3.3V
16 PERIOD JITTER (psRMS) 133MHz 12 125MHz 33.3MHz
3.3V
8
62.5MHz
4
0V
0V
0 -40 -15 10 35 60 85 TEMPERATURE (C)
2ns/div
2ns/div
DUTY CYCLE vs. TEMPERATURE
MAX9492 toc07
PERIOD JITTER vs. FREQUENCY
MAX9492 toc08
133MHz OUTPUT 0% DOWNSPREADING
MAX9492 toc09
51.0 50.5 50.0 DUTY CYCLE (%) 49.5 49.0 48.5 48.0 47.5 47.0 -40 -15 10 35 60 133MHz 125MHz 62.5MHz 33.3MHz
20
16 PERIOD JITTER (psRMS)
12
10dB/REF 0dBm RBW = 10kHz VBW = 10kHz ATN = 20dB CENTER = 133MHz SPAN = 4MHz
8
4
0 85 25 50 TEMPERATURE (C) 75 100 FREQUENCY (MHz) 125 150
133MHz OUTPUT WITH 0% AND 1.25% DOWNSPREADING
MAX9492 toc10
133MHz OUTPUT WITH 0% AND 2.5% DOWNSPREADING
MAX9492 toc11
10dB/REF 0dBm VBW = 1kHz CENTER = 133MHz
RBW = 100kHz ATN = 20dB SPAN = 15MHz
10dB/REF 0dBm VBW = 1kHz CENTER = 133MHz
RBW = 100kHz ATN = 20dB SPAN = 15MHz
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Multiple-Output Clock Generator with Spread Spectrum MAX9492
Pin Description
PIN 1 2 3 4 5, 13, 16 6 7 8, 20 9 10 11 12 14 15 17 18 19 EP NAME GNDA X1 X2 VDDA VDD SCL SDA GND CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 SSC SA1 SA0 GND Analog Ground Crystal Connection or Clock Input. If using a 25MHz crystal, connect it to X1 and X2. If using a reference clock, connect the clock signal to X1 and leave X2 floating. See the Typical Operating Circuit. Power-Supply Input for Analog Circuits. Bypass to GNDA with a 0.1F capacitor. Power-Supply Input for Digital Circuits. Bypass to GND with a 0.1F capacitor. Serial Clock Input. Serial interface clock. Serial Data I/O. Data I/O of serial interface. Digital Ground Clock 1 Output. Buffered reference clock output. Clock 2 Output. Frequency-selectable clock output. Clock 3 Output. Frequency-selectable clock output. Clock 4 Output. Frequency-selectable clock output. Clock 5 Output. Frequency-selectable clock output. Clock 6 Output. Frequency-selectable clock output. Spread-Spectrum-Select Input. Selects the spectrum-spread percentage. When SSC is low, spread spectrum is disabled. When SSC is floating, spread spectrum is set to -1.25%. When SSC is high, spread spectrum is set to -2.5%. Address-Select Inputs for Serial Interface. SA0 and SA1 select the serial interface address, as shown in Table 1. SA0 and SA1 are three-level inputs, making nine possible address combinations. Exposed pad. Connect to GND. FUNCTION
Block Diagram
VDDA VDD
SCL SDA SA0 SA1
I 2C
CLK1
MUX 266MHz PLL1 25MHz OSC X2 250MHz PLL2 DIVIDE BY 2, 3, 4, 5, 10 MUX DIVIDE BY 2, 4, 8
CLK2
X1
CLK5
SSC
SPREAD SPECTRUM
MAX9492
MUX
CLK6
AGND
GND
6
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Multiple-Output Clock Generator with Spread Spectrum
Detailed Description
The MAX9492 frequency synthesizer is designed to generate multiple clocks for clock distribution in network routers or switches. The device provides a total of six buffered clock outputs (CLK1 to CLK6). CLK1 is the buffered output of the reference clock. CLK2 through CLK6 are independently programmable to generate eight different frequencies based on a 25MHz input crystal: 133, 125, 83, 66, 62.5, 50, 33, and 25MHz. All the outputs are LVCMOS single-ended signals. Select the MAX9492's output frequency by programming on-chip registers through the I2C interface. The MAX9492 also features spread-spectrum capability to reduce EMI. Output frequency spectrum can be downspread by -2.5% or -1.25%. The 25MHz reference comes from either a crystal or an external clock. The MAX9492 incorporates two PLLs with two internal loop filters. The MAX9492 operates from a 3.3V supply.
Power-Up State
At power-up, the CLK1 output is enabled and free running, the CLK2 to CLK4 outputs are set at 33.3MHz, and the other CLK outputs are disabled at logic-low. The output states can be overridden by writing to the registers through the I2C interface.
MAX9492
Serial Interface
The MAX9492 is programmed through its I 2C serial interface. This interface has a clock, SCL, and a bidirectional data line, SDA. In an I2C system, a master, typically a microcontroller, initiates all data transfers to and from slave devices, and generates the clock to synchronize the data transfers. The MAX9492 operates as a slave device. The timing of the SDA and SCL signals is detailed in Figure 1. SDA operates as both an input and an open-drain output. A pullup resistor, typically 4.7k, is required on SDA. SCL operates only as an input. A pullup resistor, typically 4.7k, is required on SCL. START and STOP Conditions A master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 2). When communication is complete, a master issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission.
Reference Frequency Input
The MAX9492 requires a reference frequency. The reference can be a 25MHz crystal or an external clock signal. If using a 25MHz crystal, connect it across X1 and X2, and connect loading capacitors from X1 and X2 to GND (refer to the crystal manufacturer's specification). If using an external clock, connect the signal to X1 and leave X2 floating.
SDA
tBUF tSU,DAT tLOW SCL tHD,DAT tSU,STA tHD,STA tSU,STO
tHIGH tHD,STA
tR tF
START CONDITION
REPEATED START CONDITION
STOP CONDITION
START CONDITION
Figure 1. Serial-Interface Timing Diagram
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7
Multiple-Output Clock Generator with Spread Spectrum MAX9492
NOT ACKNOWLEDGE SDA 1 1 A4 A3 A2 A1 A0 R/W ACK
SCL
MSB
ACKNOWLEDGE LSB
START
Figure 2. I2C Address and Acknowledge
Bit Transfer One data bit is transferred during each SCL clock cycle. SDA must remain stable during the high period of SCL, as changes in SDA while SCL is high are START and STOP control signals. Idle the interface by pulling both SDA and SCL high. After 8 bits are transferred, the receiving device generates an acknowledge signal by pulling SDA low for the entire duration of the 9th clock pulse. If the receiving device does not pull SDA low, a not acknowledge is indicated (Figure 2).
Device Address
The MAX9492 features a 7-bit device address, configured by the two three-level address inputs, SA1 and SA0. To select the device address, connect SA1 and SA0 to VDD, GND, or leave floating, as indicated in Table 1. The MAX9492 has nine possible addresses, allowing up to nine MAX9492 devices to share the same interface bus.
Writing to the MAX9492
Writing to the MAX9492 begins with a START condition (Figure 3). Following the START condition, each pulse on SCL transfers 1 bit of data. The first 7 bits comprise the device address (see the Device Address section). The 8th bit is low to indicate a write operation. An acknowledge bit is then generated by the MAX9492, signaling that it recognizes its address. The next 8 bits form the register address byte (Table 2) and determine which control register receives the following data byte. The MAX9492 then generates another acknowledge bit. The data byte is then written into the addressed register of the MAX9492. An acknowledge bit by the MAX9492 followed by a required STOP condition by the master completes the communication. To write to the device again, the entire write procedure is repeated; I2C burstwrite mode is not supported by the MAX9492.
Table 1. Device I2C Address Selection
SA0 Open Low High Open Low High Open Low High SA1 Open Open Open Low Low Low High High High DEVICE ADDRESS 110 1000 110 0100 110 0010 110 1100 110 1001 111 0000 111 0001 111 0010 111 0100
8
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Multiple-Output Clock Generator with Spread Spectrum MAX9492
MASTER-WRITE DATA STRUCTURE START S 1 1 DEVICE ADDRESS A4 A3 A2 A1 A0 R/W 0 REGISTER ADDRESS ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK D7 D6 D5 DATA IN D4 D3 D2 D1 STOP D0 ACK P
MASTER-READ DATA STRUCTURE START S 1 1 DEVICE ADDRESS A4 A3 A2 A1 A0 R/W 0 REGISTER ADDRESS ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK DEVICE ADDRESS RS 1 1 A4 A3 A2 A1 A0 R/W 1 ACK D7 D6 D5
DATA OUT D4 D3 D2 D1 D0 ACK
STOP P
S = START CONDITION A_ = DEVICE ADDRESS ACK = ACKNOWLEDGE ACK = NOT-ACKNOWLEDGE
RA_ = REGISTER ADDRESS D_ = DATA P = STOP CONDITION RS = REPEATED START
DATA DIRECTION = MASTER TO SLAVE = SLAVE TO MASTER
Figure 3. I2C Interface Data Structure
Reading from the MAX9492
Reading from the MAX9492 registers begins with a START condition and a device address with the write bit set low, then the register address that is to be read, followed by a repeated START condition and a device address with the write bit set high, and finally the data are shifted out (Figure 3). Following a START condition, the first 7 bits comprise the device address. The 8th bit is low to indicate a write operation (to write in the following register address). An acknowledge bit is then generated by the MAX9492, signaling that it recognizes its address. The next 8 bits form the register address, indicating the location of the data to be read, followed by another acknowledge, again generated by the MAX9492. The master then produces a repeated START condition and readdresess the device, with the R/W bit high to indicate a read operation (Figure 3). The MAX9492 generates an acknowledge bit, signaling that it recognizes its address. The data byte is then clocked out of the MAX9492. A final not-acknowledge bit, generated by the master (not required), and a STOP condition, also generated by the master, complete the communication. To read from the device again, the entire read procedure is repeated; I 2 C burst-read mode is not supported by the MAX9492.
Device Control Registers
The MAX9492 has eight control registers. The register addresses and functions are shown in Table 2. The first seven registers are used to set the six outputs, with register 0x00 controlling all outputs simultaneously, and the rest are mapped to individual outputs. All other addresses are reserved and are not to be used.
Table 2. Register Address Mapping
REGISTER ADDRESS 00 01 02 03 04 05 06 All others OUTPUT PORT Broadcast to all CLK registers CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 Reserved
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Multiple-Output Clock Generator with Spread Spectrum MAX9492
Setting the Clock Frequencies
Each CLK_ output has an associated control register. The contents of the registers determine the frequencies of their associated outputs. Table 3 provides the frequency mapping for the registers. CLK1 only responds to the 25MHz and high-impedance settings in Table 3. For example, writing 03h to the CLK1 control register does not change CLK1's output frequency to 133.3MHz. The CLK1 output continues to output a buffered reference clock signal.
Spread-Spectrum Control
The MAX9492 features spread-spectrum output structures to spread radiated emissions over the frequency band. A programmable triangle-wave generator injects an offset element into the master oscillator to dither its output by -1.25% or -2.5%. The dither is controlled by the SSC input. When SSC is low, spread spectrum is disabled. When SSC is floating, spread spectrum is set to -1.25%. When SSC is high, spread spectrum is set to -2.5%.
Power Supply
Table 3. Output Frequency Selection for CLK1-CLK6
BITS IN CLKn REGISTERS 00 01 02 03 04 05 06 07 08 0F OUTPUT FREQUENCY (MHz) Logic-Low 133.3 125 83.3 66.6 62.5 50 33.3 25 High Impedance
The MAX9492 uses a 3.0V to 3.6V power supply connected to VDD, and 3.0V to 3.6V connected to VDDA. Bypass V DDA and V DD at the device with a 0.1F capacitor. Additionally, use bulk bypass capacitors of 10F where power enters the circuit board.
Applications Information
Board Layout Considerations
As with all high-frequency devices, board layout is critical to proper operation. Place the crystal as close as possible to X1 and X2, and minimize parasitic capacitance around the crystal leads. Ensure that the exposed pad makes good contact with GND.
Chip Information
PROCESS: BiCMOS
Typical Operating Circuit
+3.3V 0.1F VDDA VDD 0.1F VDD X1 10pF 25MHz 10pF X2 SERIAL INTERFACE SDA SCL SA0 SA1 SSC AGND 0.1F VDD +3.3V 0.1F
Pin Configuration
TOP VIEW
CLK5
CLK6 CLK4 CLK3
15 VDD SSC 16 17 18 19 20
14
13
VDD
12
11 10 9 CLK2 CLK1 GND SDA SCL
MAX9492
CLK1 CLOCK OUTPUTS CLK6
SA1 SA0 GND
MAX9492
EXPOSED PADDLE (GND)
8 7 6
1
GND
2
X1
3 X2
4 VDDA
5 VDD
GNDA
THIN QFN
10
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Multiple-Output Clock Generator with Spread Spectrum
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 D D/2 MARKING k L
C L
MAX9492
b D2/2
0.10 M C A B
XXXXX
E/2 E2/2 E (NE-1) X e
C L
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
H
1 2
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 T4055-1
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
-0.15
DOWN BONDS ALLOWED
A A1 A3 b D E e k L L1 N ND NE JEDEC
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.25 - 0.25 0.20 REF. 0.20 REF. 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.50 BSC. 0.40 BSC. 0.50 BSC. - 0.25 0.35 0.45 0.25 - 0.25
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.20
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** ** **
NO YES NO NO YES NO YES NO NO YES YES NO NO YES YES NO NO YES NO NO YES
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 - 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 40 10 10 -----
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3, AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", -0.05.
3.30 3.40 3.20
** SEE COMMON DIMENSIONS TABLE
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
H
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
QFN THIN.EPS

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